The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor.
Device structures for a field-effect transistor include a source, a drain, a channel situated between the source and drain, and a gate structure including a gate electrode and a gate dielectric separating the gate electrode from the channel. A gate voltage applied to the gate electrode is used to provide switching that selectively connects the source and drain to each other through the channel. The channel of a planar field-effect transistor is located beneath the top surface of a substrate on which the gate structure is supported.
A fin-type field-effect transistor (FinFET) is a non-planar device structure that may be more densely packed in an integrated circuit than planar field-effect transistors. A FinFET may include a fin consisting of a body of semiconductor material, heavily-doped source/drain regions formed in sections of the body, and a gate electrode that wraps about a channel located in the fin body between the source/drain regions. The arrangement between the gate structure and fin body improves control over the channel and reduces the leakage current when the FinFET is in its ‘Off’ state in comparison with planar transistors. This, in turn, enables the use of lower threshold voltages than in planar transistors, and results in improved performance and reduced power consumption.
Stacked nanowire or nanosheet field-effect transistors have been developed as a type of FinFET that may permit additional increases in packing density. A stacked nanosheet field-effect transistor may include multiple nanosheets arranged in a three-dimensional array on a substrate with a gate stack formed on the nanosheet channel regions. The gate stack may surround all sides of the channel region of each nanosheet in a gate-all-around arrangement.